Governor Wolf Joins Front Lines in Battle Against Spotted Lanternfly July 16, 2019 Environment, Press Release Harrisburg, PA – Governor Tom Wolf today joined Agriculture Secretary Russell Redding and representatives from the Pennsylvania Department of Agriculture (PDA), Penn State University, and USDA at a Harrisburg site populated with Spotted Lanternflies to view the treatment being conducted across the commonwealth.“Although Pennsylvania had the unlucky fate of being the first state in the nation to be visited by the Spotted Lanternfly, we faced that challenge head-on and have made incredible strides in containment and control,” said Gov. Wolf. “This is a team effort and all hands are on deck, committed to protecting Pennsylvania’s agricultural products, preserving our quality of life, and keeping commerce flowing here in the commonwealth.”Under the governor’s PA Farm Bill – a package of legislation designed to expand and protect agriculture infrastructure – the Pennsylvania Rapid Response Disaster Readiness Account will provide $3 million toward the containment of the Spotted Lanternfly. This is the second year in a row the governor has allocated funding in the state budget to increase spotted lanternfly detection, control, and eradication efforts. Over the past few years the administration has allocated more than $10 million to protect Pennsylvania business and agriculture. Additionally, USDA recently dedicated more than $6.2 million in new funding to Pennsylvania’s efforts.This May, PDA introduced the Spotted Lanternfly permit system to train businesses and employees on recognizing the life stages of the Spotted Lanternfly. Since then, the department has issued more than 900,000 permits to businesses that travel in and out of the quarantine area. Additionally, PDA and USDA teams continue to assess and treat high-risk properties, with survey teams scouting for insects across the state after receiving reports of sightings outside of the quarantine area. Penn State has taken the lead on conducting outreach and research.“Pennsylvania’s progress in controlling the Spotted Lanternfly is due in part to the historic partnership we’ve made with USDA and Penn State and the critical funding we received through the state and federal budgets,” said Sec. Redding. “However, it’s important that Pennsylvanians remember that they play a significant role in this fight. They can treat their property with approved sprays, band their trees, or even use something as simple as a fly swatter to help control populations right in their own backyard.”Businesses can obtain a Spotted Lanternfly permit at https://extension.psu.edu/spotted-lanternfly-permit-training. Homeowners with questions about treatment, including approved sprays, can learn more through Penn State Extension at http://extension.psu.edu/spotted-lanternfly.For more information on the Spotted Lanternfly, visit https://www.agriculture.pa.gov/spottedlanternfly. SHARE Email Facebook Twitter
Senior Hurling Coach Declan Fanning is expecting a real good battle when Tipperary take on Wexford in the National League Semi final this weekend.The Premier set up the encounter with Davy Fitzgerald’s side after victory over Offaly a fortnight ago while Wexford come into the clash buoyed by defeat of hurling giants Kilkenny.Killenaule club man Fanning says league matches like these are essential of testing out players ahead of their Championship start against Cork Throw in at Nowlan Park on Sunday is at 4 and Tipp FM will have full live coverage in association with the Donal Ryan Motor Group – Nenagh, Thurles & Roscrea and Arabawn Store, Tyone, Nenagh.
Dr Peter David Phillips is now the official president of Jamaica’s opposition People’s National Party (PNP).Phillips took the oath of office during a ceremony at King’s House in St Andrew, on Monday morningThe former finance minister was handed the reigns of the PNP by outgoing President Portia Simpson Miller two Sundays ago at a special delegates’ conference held at the National Arena. He is the fifth president of the 79-year-old party.Phillips will seek to reconcile his party which has been affected by infighting over the past year. He has vowed to re-energise the country’s youth in a bid to attract them to the party as well as lead a viable Opposition.Finance last served as finance minister but has also served as Minister of Health, Transport and National Security.He lost twice to Simpson Miller in presidential races.
Leave a Reply Cancel reply You must Register or Login to post a comment. This site uses Akismet to reduce spam. Learn how your comment data is processed. Share this:TwitterFacebookLinkedInMoreRedditTumblrPinterestWhatsAppSkypePocketTelegram Tags: Digital, Manufacturing Continue Reading Previous Experience virtual reality at ESC MinneapolisNext Self-installing an automotive driver assistance system While talking about the future of wearable technology, Ralph Osterhout (CEO, The Osterhout Design group) made a crisp and relevant observation: “What won’t work is a bulky device that distances people from their environment. If you’re talking about something that makes you look like a hammer-head shark with wires? Then, no. It’s not going to work.” ( source) This clearly indicates the future course of innovation in wearable technology. It’s loud and clear that to be successful, a wearable electronic item has to be small while maintaining performance.To reduce footprint and, consequently, overall board-space, microcontrollers are migrating to smaller process nodes every successive generation. At the same time they are evolving to perform more complex and powerful operations. The need for increasing cache memory becomes imminent as operations become more complex. Unfortunately, with every new process node, increasing the embedded cache (embedded SRAM) becomes challenging for multiple reasons including higher SER, lower yield, and increased power consumption. In addition, customers also have customized SRAM requirements. For an MCU maker to provide all the possible cache sizes would require them to have a portfolio that is too big to be manageable. This drives the need for limiting the embedded SRAM on the controller die and instead caching through an external SRAM.However, using an external SRAM challenges the very process of miniaturization as external SRAMs occupy significant board space. Because of its six-transistor structure, reducing an external SRAM size by migrating it to smaller process nodes will invite the same problems that plague miniaturizing embedded SRAMs.This brings us to the next alternative to this age-old problem: reduce the chip package to die size ratio in the external SRAM. Typically the size of a packaged SRAM chip is many times (up to 10x) the size of the die. One prevalent way of addressing the problem is to not use a packaged SRAM chip at all. Instead, it makes sense to take the SRAM die (1/10th the size of an SRAM chip) and package it together with the MCU die using sophisticated multi-chip packaging (MCP) or 3D packaging techniques (also known as SiP or System-in-Package). However, this method requires significant investment and is viable only for the largest of manufacturers. From a design stand-point, it also reduces flexibility since the components in a SiP aren’t easily replaceable. For example, if there is a new technology SRAM available, we cannot easily replace the SRAM die in the SiP easily. To replace any die within the package, the entire SiP would have to be re-qualified. Re-qualification requires reinvestment and additional time.So is there a way to save on board-space, while keeping the SRAM out of the MCU and not getting into the hassles of MCP? Going back to the die to chip size ratio, we do see a scope for significant improvement. Why not check whether there can be a package that can stick closer to the die? In other words, if you can’t eliminate the package, reduce the size ratio instead.The most advanced approach currently is to reduce the packaged die size by using WLCSP (wafer level chip scale packaging). WLCSP refers to the technology of assembling individual units in packages after dicing them from a wafer. The device is essentially a die with an array pattern of bumps or balls without using any bond wires or interposer connections. By specification, a chip scale package part has an area that is at the most 20% larger than the die. Today the process has reached a level of innovation whereby fabrication plants produce CSP devices without increasing the area of the die (only increasing the thickness slightly to fit the bumps/balls).Figure. Wafer level chip scale packaging (WLCSP) offers the most advanced approach to reducing packaged die size. The WLCSP shown here was developed at Deca Technologies and does not increase the area of the die comprising it. (Source: Deca Technologies/Cypress Semiconductor) CSP has certain advantages over the bare die. CSP devices are easier to test, handle, assemble and reword. They also have enhanced thermal conduction characteristics. And when dies shift to newer process nodes, the size of the CSP can be standardized while dies shrink. This ensures that a CSP part can be replaced by a newer generation CSP part without the any of complications associated with replacing a die.It is quite clear that these space savings are significant when it comes to the requirements of wearables and portable electronics. For example, a 48-ball BGA used by memories in many wearable devices today has the dimensions 8mm x 6mm x 1mm (48mm3 ). By comparison, the same part in a CSP type package has the dimensions 3.7mm x 3.8mm x 0.5mm (7mm3 ). In other words, it is possible to reduce the volume by 85%. This savings can be used to reduce the portable device’s PCB area and thickness. For this reason, there is renewed demand for WLCSP-based devices beyond just SRAM from wearable and IoT (Internet of Things) manufacturers. For more information on designing with WLCSP, designers can refer to Getting Started with Chip Scale Packages.